The invention relates to the general field of magnetic memories with particular reference to programming MTJ cells.
The principle governing the operation of the memory cells in magnetic RAMs is the change of resistivity of certain materials in the presence of a magnetic field (magneto-resistance). Magneto-resistance can be significantly increased by means of a structure known as a spin valve. The resulting increase (known as Giant Magneto-Resistance or GMR) derives from the fact that electrons in a magnetized solid are subject to significantly less scattering by the lattice when their own magnetization vectors (due to spin) are parallel (as opposed to anti-parallel) to the direction of magnetization of their environment.
The key elements of a spin valve are a low coercivity (free) ferromagnetic layer, a non-magnetic spacer layer, and a high coercivity ferromagnetic layer. The latter is usually formed out of a soft ferromagnetic layer that is pinned magnetically by an associated antiferromagnetic layer. When the free layer is exposed to an external magnetic field, the direction of its magnetization is free to rotate according to the direction of the external field. After the external field is removed, the magnetization of the free layer will stay at a direction, which is dictated by the minimum energy state, determined by the crystalline and shape anisotropy, coupling field and demagnetization field. If the magnetization direction of the pinned layer is parallel to the free layer, electrons passing between the free and pinned layers, suffer less scattering. Thus, the resistance at this state is lower, when current flows along the film plain. If, however, the magnetization of the pinned layer is anti-parallel to the free layer, electrons passing from one layer into the other will suffer more scattering so the resistance of the structure will increase. The change in resistance of spin valve is typically 8-15%.
The simple sandwich structure of ferromagnetic layer-thin conductor-ferromagnetic layer can be used as memory element. In this structure, there is no anti-ferromagnetic layer, thus, neither of the two ferromagnetic layers is pinned. This kind of memory cell is called a pseudo-spin valve memory cell. Both are free to switch magnetization under external field. One of the ferromagnetic layers is thicker than the other, the thicker one switches magnetization direction at a higher external magnetic field.
Of special interest for the present invention is the magnetic tunneling junction (MTJ) in which the layer that separates the free and pinned layers is a non-magnetic insulator, such as alumina or silica. Its thickness needs to be such that it will transmit a significant tunneling current. The principle governing the operation of the MTJ cell in magnetic RAMs is the change of resistivity of the tunnel junction between two ferromagnetic layers. When the magnetization of the two ferromagnetic layers is in opposite directions, the tunneling resistance increases due to a reduction in the tunneling probability. The change of resistance is typically 40%, which is much larger than for GMR devices.
A magnetic tunnel junction device is made up of three basic layers. A top ferromagnetic (FM) layer, a tunnel oxide insulating layer and a bottom FM layer. The magnetization of the top FM layer is free to switch states while the bottom electrical conducting FM layer is pinned, usually by an antiferromagnetic (AF) material, such as PtMn or NiMn. We refer to those layers that are below the tunnel junction as the base layer. Depending on the order in which layers are deposited, the base layer could be a ferromagnetic layer on an antiferromagnetic layer on a seed layer or it could be a single ferromagnetic layer. Typically, the base layer is electrically conductive and the thickness of the base layer is less than 500 xc3x85.
The cell states are programmed by applying an external magnetic field to switch the magnetization of the free layer. A current in the program line under a cell generates the program field.
A problem associated with the programming of MRAM (magnetic random access memory) has been that the required current is orders of magnitude larger than that needed for many other memory devices such as SRAMs or DRAMs, being in the range of 6-10 mA. Furthermore, cell size does not scale with lithography. For such large program currents, the width of the program lines of the cell is much greater than the minimal wire widths allowed by the design rules. In addition, today""s MOSFET switches can only provide 0.2-0.5 mA for a gate width of 1 xcexcm so, to switch a 10-mA current, a MOSFET must be designed with a gate width greater than 20 xcexcmxe2x80x94which is too large. Thus, it is very important to minimize the program current in MRAMs.
From the point of view of data retention, MRAM cells must maintain a finite switching threshold such that the probability of an accidental cell switch by the thermal energy is negligible. The probability of accidentally switching is proportional to Exp(xe2x88x92E/kT), where E is the barrier energy between the two states, and E=Hc*V, Hc being the coercivity and V the physical volume of the free layer material of the cell. The barrier is a function of cell material and cell geometry. Typically, a MRAM cell must be designed to satisfy Exe2x89xa640kT, where k is Boltzmann""s constant and T is the absolute temperature of the cell. Hence MRAM cells must not be designed only with arbitrarily small switch fields.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,072,718 (Abraham et al.) shows a MRAM cell structure with MTJ structures while, in U.S. Pat. No. 6,368,878 B1, Abraham et al. disclose a MRAM cell structure with MTJ structures. Gill et al. (U.S. Pat. No. 6,219,212 B1) discloses a MRAM cell that includes an insulating AFM and Parkin et al. (U.S. Pat. No. 6,166,948) discusses MRAM cells and MTJ cells. None of these references disclose local heating of individual memory elements.
U.S. Pat. No. 6,385,082 (Abraham et al.) needs more detailed discussion. This reference teaches an array of electrically conducting bit lines and word lines. A storage cell is located at each intersections, each storage cell including at least one magnetically reversible region characterized by a magnetization state which can be more easily reversed by changing its temperature, together with a temperature change generator capable of changing the temperature of a single, selected storage cell as needed. To select a cell, it is preferable to use a brief pulse of tunneling current passing between the appropriate bit and word lines. This provides sufficient Joule heating to facilitate a change in the magnetization state of the selected storage cell (which preferably comprises a ferrimagnetic material).
As will become apparent below, this reference does not make use of the write current pulse to provide the heating current. More specifically, in the present invention, there may be two write currents in two different lines. One or both lines may be used to generate the heat needed to switch a cell. The magnetic field that is generated when current passes through this line(s) can be Hassist or Hdata. In particular, our write current does not flow through the tunnel junction, as taught in U.S. Pat. No. 6,385,082. Our heating current flows in the plane of the program line (see first embodiment below) and flows in the plane of the pinned layer (see second embodiment below). Thus, in the present invention, a high resistance region in the cell acts as the heat generator under a write current, not the tunnel junction. The present invention also discloses placing high thermal resistivity material around the cell to prevent heat from leaking out to the neighboring cells. This refinement is not taught in the prior art.
It has been an object of at least one embodiment of the present invention to provide a GMR based memory element that can be programmed using less current than needed by devices of the prior art.
Another object of at least one embodiment of the present invention has been that neighboring devices not be disturbed when said element is programmed.
Still another object of at least one embodiment of the present invention has been that said elements be addressable by conventional means.
A further object of at least one embodiment of the present invention has been to provide a process for performing said programming operation.
These objects have been achieved by adding heating lines to the standard array configuration. These lines provide local heating sources located in close proximity to the memory elements so that when a given element is being programmed it is also being heated. The effect of the heating is to lower the threshold for magnetization so that a lower field (and hence reduced program current) can be used. The heating line function may also be implemented as part of the bit, word, or programming functions. For the latter case, a further refinement is to make the base layers of the element also serve as the heating element This approach is particularly effective when applied to magnetic tunnel junctions since the tunneling insulator also acts as a thermal insulator during heating.